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Integrated Circuit Systems, Inc.
ICS9248-126
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM & K6
Recommended Application: Motherboard Single chip clock solution for Pentium II/III and K6 processors, using SIS540/SIS630 style chipset. Output Features: * 3- CPUs @ 2.5/3.3V, up to 166MHz. * 14 - SDRAM @ 3.3V * 7- PCI @3.3V, * 1- 48MHz, @3.3V fixed. * 1- 24/48MHz, @3.3V selectable by I2C (Default is 24MHz). * 2- REF @3.3V, 14.318MHz. Features: * Up to 166MHz frequency support * Support FS0-FS3 trapping status bit for I2C read back. * Support power management: CPU, PCI, SDRAM stop and Power down Mode form I2C programming. * Spread spectrum for EMI control (0 to -0.5%, 0.25%). * FS0, FS1, FS3 must have a internal 120K pull-Down to GND. * Uses external 14.318MHz crystal Skew Specifications: * CPU - CPU: < 175ps * SDRAM - SDRAM < 500ps * PCI - PCI: < 500ps * CPU - SDRAM: < 500ps * CPU - PCI: 1 - 4ns
Pin Configuration
VDDREF 1 * REF0/FS3 GND X1 X2 VDDPCI *PCICLK0/FS1 *PCICLK1/FS2 PCICLK2 GND PCICLK3 PCICLK4 PCICLK5 PCICLK6 VDDSDR GND SDRAM0 SDRAM1 VDDSDR SDRAM2 SDRAM3 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1 VDDLCPU CPUCLK0 CPUCLK1 GND CPUCLK2 VDDSDR SDRAM13 SDRAM12 GND SDRAM11 SDRAM10 VDDSDR SDRAM9 SDRAM8 GNDSDR SDRAM7 SDRAM6 VDDSDR SDRAM5 SDRAM4 VDDSDR 1 48MHz/FS0* 24_48MHz/CPU2.5_3.3#*
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND. 1 These are double strength.
Block Diagram
PLL2 /2 X1 X2 XTAL OSC 48MHz 24_48MHz
Functionality
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 66.6 100.0 150.0 133.3 66.8 100.0 100.0 133.3 66.8 97.0 70.0 95.0 95.0 112.0 97.0 96.2 SDRAM (MHz) 100.0 100.0 100.0 100.0 133.6 133.3 150.0 133.3 66.8 97.0 105.0 95.0 126.7 112.0 129.3 96.2 PCICLK (MHz) 33.3 33.3 37.5 33.3 33.4 33.3 37.5 33.3 33.4 32.3 35.0 31.7 31.7 37.3 32.2 32.1
2
REF (1:0)
PLL1 Spread Spectrum FS(3:0) 4
CPU CLOCK DIVDER SDRAM CLOCK DIVDER
3
CPUCLK (2:0)
LATCH
14
SDRAM (13:0)
Control CPU2.5_3.3# SDATA SCLK Logic Config. Reg.
PCI CLOCK DIVDER
7
PCICLK (6:0)
9248-126 Rev C 9/6/00 Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9248-126
ICS9248-126
General Description
The ICS9248-126 is the single chip clock solution for Desktop/Notebook designs using the SIS 540/630 style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-126 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDDREF = REF, X1, X2 VDDPCI = PCICLK_F, PCICLK VDDSDR = SDRAM, supply for PLL core, VDD48 = 48MHz, 24MHz VDDLCPU = CPUCLKs
Pin Configuration
PIN NUMBER 1, 6, 15, 19, 27, 30, 36, 42 2 3, 10, 16, 22, 33, 39, 44 4 5 7 8 14, 13, 12, 11, 9 41, 40, 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17 23 24 25 26 43, 45, 46 47 48 PIN NAME VDD REF0 FS3 GND X1 X2 FS1 PCICLK0 FS2 PCICLK1 PCICLK (6:2) SDRAM (13:0) SDATA SCLK CPU2.5_3.3# 24_48MHz FS0 48MHz CPUCLK (2:0) VDDLCPU REF1 TYPE PWR OUT IN PWR IN OUT IN OUT IN OUT OUT OUT I/O IN IN OUT IN OUT OUT PWR OUT DESCRIPTION 3.3V Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48MHz output 14.318 MHz reference clock. Frequency select pin. Ground pin for 3V outputs. Crystal input,nominally 14.318MHz. Crystal output, nominally 14.318MHz. Frequency select pin. PCI clock outputs. Frequency select pin. PCI clock outputs. PCI clock outputs. SDRAM clock outputs Data pin for I C circuitry 5V tolerant Clock input of I2C input, 5V tolerant input Voltage select 2.5V when high - 3.3V when low Clock output for super I/O/USB default is 24MHz Frequency select pin. 48MHz output clock CPU clock outputs. Power pin for the CPUCLKs. 2.5V 14.318 MHz reference clock.
2
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ICS9248-126
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit ICS (Slave/Receiver)
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit

How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9248-126
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Description Bit7 Bit2 Bit6 Bit5 Bit4 CPU SDRAM 0 0 0 0 0 66.6 100.0 0 0 0 0 1 100.0 100.0 0 0 0 1 0 150.0 100.0 0 0 0 1 1 133.3 100.0 0 0 1 0 0 66.8 133.6 0 0 1 0 1 100.0 133.3 0 0 1 1 0 100.0 150.0 0 0 1 1 1 133.3 133.3 0 1 0 0 0 66.8 66.8 0 1 0 0 1 97.0 97.0 0 1 0 1 0 70.0 105.0 0 1 0 1 1 95.0 95.0 0 1 1 0 0 95.0 126.7 0 1 1 0 1 112.0 112.0 0 1 1 1 0 97.0 129.3 0 1 1 1 1 96.2 96.2 Bit 7, 2, Bit 6:4 1 0 0 0 0 66.8 100.2 1 0 0 0 1 100.2 100.2 1 0 0 1 0 166.0 110.7 1 0 0 1 1 100.2 133.6 1 0 1 0 0 75.0 100.0 1 0 1 0 1 83.3 125.0 1 0 1 1 0 105.0 140.0 1 0 1 1 1 133.6 133.6 1 1 0 0 0 110.3 147.0 1 1 0 0 1 115.0 153.3 1 1 0 1 0 120.0 120.0 1 1 0 1 1 138.0 138.0 1 1 1 0 0 140.0 140.0 1 1 1 0 1 145.0 145.0 1 1 1 1 0 147.5 147.5 1 1 1 1 1 160.0 160.0 0 - Frequency is selected by hardware select, Latched Inputs Bit 3 1 - Frequency is selected by Bit 7, 2, 6:4 0 - Normal Bit 1 1 - Spread Spectrum Enabled 0 - Running Bit 0 1- Tristate all outputs Bit PWD PCI 33.3 33.3 37.5 33.3 33.4 33.3 37.5 33.3 33.4 32.3 35.0 31.7 31.7 37.3 32.3 32.1 33.4 33.4 27.7 33.4 37.5 31.3 35.0 33.4 36.8 38.3 30.0 34.5 35.0 36.3 36.9 26.7 SS 0 to-0.5% 0 to-0.5% 0.25% 0 to-0.5% 0 to-0.5% 0 to-0.5% 0.25% 0 to-0.5% 0.25% 0 to-0.5% 0.25% 0.25% 0.25% 0.25% 0 to-0.5% 0 to-0.5% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25%
00010 Note1
0 1 0
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. The I2C readback for Bits 7, 2, 6:4 indicate the revision code. Note: PWD = Power-Up Default I2C is a trademark of Philips Corporation
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4
ICS9248-126
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable) Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 43 45 46 -
PWD 1 1 1 1 1 1 1 1
DESCRIPTION SEL24_48# (48MHz when set to 0) (24MHz when set to 1) R e s e r ve d R e s e r ve d R e s e r ve d CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact) R e s e r ve d
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 14 13 12 11 9 8 7
PWD 1 1 1 1 1 1 1 1
DESCRIPTION (CPU2.5_3.3#) PCICLK6 (Act/Inact) PCICLK5 (Act/Inact) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0 (Act/Inact)
Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 32 31 29 28 21 20 18 17
PWD 1 1 1 1 1 1 1 1
DESCRIPTION SDRAM 7 (Act/Inact) SDRAM 6 (Act/Inact) SDRAM 5 (Act/Inact) SDRAM 4 (Act/Inact) SDRAM 3 (Act/Inact) SDRAM 2 (Act/Inact) SDRAM 1 (Act/Inact) SDRAM 0 (Act/Inact)
BIT PIN# PWD Bit 7 25 1 Bit 6 26 1 Bit 5 41 1 Bit 4 40 1 Bit 3 38 1 Bit 2 37 1 Bit 1 35 1 Bit 0 34 1
DESCRIPTION 24_48MHz 48MHz SDRAM13 SDRAM12 SDRAM11 SDRAM10 SDRAM9 SDRAM8
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 48 1 Bit 0 2 1
Notes:
DESCRIPTION R e s e r ve d R e s e r ve d FS3# FS2# FS1# FS0# REF1 (Act/Inact) REF0 (Act/Inact)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 0 0 0 0 1 1 0
DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inferted logic load of the input frequency select pin conditions.
Note: Dont write into this register, writing into this register can cause malfunction
Third party brands and names are the property of their respective owners.
5
ICS9248-126
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND 0.5 V to V DD +0.5 V 0C to +70C 115C 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Operating IDD3.3OP66 CL = 0 pF; Select @ 66MHz Supply Current IDD3.3OP100 CL = 0 pF; Select @ 100MHz IDD3.3OP133 CL = 0 pF; Select @ 133MHz Input frequency Fi VDD = 3.3 V; 1 Input Capacitance CIN Logic Inputs CINX X1 & X2 pins 1 Transition Time Ttrans To 1st crossing of target Freq. Clk Stabilization1 TSTAB From VDD = 3.3 V to 1% target Freq. tCPU-PCI VT = 1.5 V Skew
1
MIN 2 VSS-0.3
11 27
1
MAX UNITS VDD+0.3 V 0.8 V 148 180 mA 150 180 mA 161 mA 14.318 16 MHz 5 pF 36 45 pF 3 ms 3 ms 2.39 4 ns
TYP
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Operating IDD2.5OP66 CL = 0 pF; Select @ 66.8 MHz IDD2.5OP100 CL = 0 pF; Select @ 100 MHz Supply Current IDD2.5OP133 CL = 0 pF; Select @ 133 MHz tCPU-SDRAM VT = 1.5 V; VTL = 1.25 V Skew1 VT = 1.5 V; VTL = 1.25 V tCPU-PCI 1
1
TYP 6.13 9.22 11.6 273 2.25
MAX 30
500 4
UNITS mA mA mA ps ns
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9248-126
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS 1 VO=VDD*(0.5) Output Impedance RDSP2A Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Cycle-to-cycle
1
MIN 10 10 2
TYP 36.5 29 2.85 0.31 -45 29 1.24 1.6 52.6 80.8 128
MAX UNITS 40 40 0.4 -19 2 2 62 175 250
RDSN2A1 VOH1a VOL1a IOH1a IOL1a tr1a1 tf1a1 dt1a1 tsk1a1 tjcyc-cyc1a1
VO=VDD*(0.5) IOH = -20.0 mA IOL = 12 mA VOH = 2 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
22 0.4 0.4 45
V V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP 1 Output Impedance RDSP2A VO=VDD*(0.5) 10 36.5 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Cycle-to-cycle RDSN2A VOH1B VOL1B IOH1B IOL1B 1 tr1B 1 tf1B 1 dt1a 1 tsk1a 1 tjcyc-cyc1B 1 tjcyc-cyc1B
1
MAX UNITS 40 40 0.4 -21 1.6 1.6 55 175 250 350
VO=VDD*(0.5) IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.25 V CPU, SDRAM Synchronous VT = 1.25 V CPU, SDRAM Asynchronous
10 2
19
45
29 2.3 0.31 -39 26 1.03 1.26 51.7 66.1 170 124.5
V V mA mA ns ns % ps ps ps
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9248-126
Electrical Characteristics - 48MHz, REF_0
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time 48MHz Fall Time 48MHz Duty Cycle 48MHz Rise Time REF_0 Fall Time REF_0 Duty Cycle REF_0 Jitter, 48MHz Jitter, REF_0
1 1 1 1 1 1
MIN 12 12 2.4
TYP 21 21 3.3 0.17 -62 57 1.78 1.92
MAX UNITS 55 55 0.4 -22 2 2 55 2 2 55 700 1500
RDSP1
1 1
VO=VDD*(0.5) VO=VDD*(0.5) IOH = -18 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
RDSP1 VOH2 VOL2 IOH2 IOL2 tr2 tf2 dt2 tr2 tf2 dt2 tjcyc2

V V mA mA ns ns % ns ns % ps ps
16
45
52 1.32 1.56
45 -350
tjcyc2
52.2 500.6 1243
Electrical Characteristics - REF_1;24/48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 20 pF PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time 24_48MHz Fall Time 24_48MHz Duty Cycle 24_48MHz Rise Time REF_1 Fall Time REF_1 Duty Cycle REF_1 Jitter, 24_48MHz Jitter, REF_1
1 1 1 1 1 1 1
MIN 20 20 2.4
TYP 42 43 2.6 0.3 -26 22 1.75 1.88
MAX UNITS 60 60 0.4 -22 4 4 55 4 4 55 1000 1500
RDSP5
1
VO=VDD*(0.5) Output P VO=VDD*(0.5) Output N IOH = -14 mA IOL = 6mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
RDSN51 VOH4 VOL4 IOH4 IOL4 tr4 tf4 dt4 tr4 tf4 dt4 tjcyc4 tjcyc4

V V mA mA ns ns % ns ns % ps ns
16
45
52 2.22 2.43
45 -1
51.1 727 1208
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-126
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
MIN 12 12 2.4
TYP 21 21 3.3 0.17 -62 43 1.62 1.81
MAX UNITS 55 55 0.4 -33 2.2 2.2 55 500 350
RDSP1
1 1
VO=VDD*(0.5) VO=VDD*(0.5) IOH = -18 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
RDSP1 VOH2 VOL2 IOH2 IOL2 tr2 tf2 dt2 tsk2 tjcyc2

V V mA mA ns ns % ps ps
38
Duty Cycle
45 -350
49.8 200 306
Skew Jitter, Cycle-to-cycle
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle RDSP2A
1 1
TYP 17 18 2.9 0.32 -73 50 1.14 1.38 51.8
MAX UNITS 20 20 0.4 -40 2 2 57
VO=VDD*(0.5) VO=VDD*(0.5) IOH = -25 mA IOL = 20 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V
10 10 2.4
RDSN2A VOH3 VOL3 IOH3 IOL3 Tr31 Tf31 Dt31

V V mA mA ns ns %
41 0.4 0.4 47
Skew1(0-1,2,4,5,7,10,11) Skew (0-6,6,8,9,12,13) Jitter, Cycle-to-cycle
1
Tsk1 Tsk1 tjcyc
VT = 1.5 V VT = 1.5 V VT = 1.5 V
155.5 298.5 369.17
250 500 650
ps ps ps
1
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
ICS9248-126
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248126 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS9248-126
General Layout Precautions: 1) Use a ground plane on the top routing layer of the PCB in all areas not used by traces. 2) Make all power traces and ground traces as wide as the via pad for lower inductance.
Ferrite Bead VDD
C2 22F/20V Tantalum
C2 22F/20V Tantalum
Ferrite Bead VDD
1 2 3
C1
48 47
C3
2.5V Power Route
46
1
4 5 6 7 8
45
C3
Clock Load
Notes: 1 All clock outputs should have provisions for a 15pf capacitor between the clock output and series terminating resistor. Not shown in all places to improve readability of diagram. 2 Optional crystal load capacitors are recommended. They should be included in the layout but not inserted unless needed.
C1 2
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
3.3V Power Route Ground
3.3V Power Route
9 10 11 12 13 14 15
Component Values: C1 : Crystal load values determined by user C2 : 22F/20V/D case/Tantalum AVX TAJD226M020R C3 : 15pF capacitor FB = Fair-Rite products 2512066017X1 All unmarked capacitors are 0.01F ceramic
16 17 18 19 20 21 22 23 24
Connections to VDD:
= Routed Power = Ground Connection Key (component side copper) = Ground Plane Connection = Power Route Connection = Solder Pads = Clock Load
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ICS9248-126
SY MBOL
In Millimeters COMMON DIMENSIONS MIN MA X 2.413 0.203 0.203 2.794 0.406 0.343
In Inches COMMON DIMENSIONS MIN MA X .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N V A RIA TIONS N 28 34 48 56 64
0.127 0.254 SEE V A RIA TIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE V A RIA TIONS .395 .291 .015 .420 .299 .025
0.635 BA SIC 0.508 1.016 SEE V A RIA TIONS 0 8
0.025 BA SIC .020 .040 SEE V A RIA TIONS 0 8
D mm. MIN 9.398 11.303 15.748 18.288 20.828 MA X 9.652 11.557 16.002 18.542 21.082 MIN .370 .445 .620 .720 .820
D (inch) MA X .380 .455 .630 .730 .830
6/1/00 R E VB
J E DEC MO- 118 DOC# 10- 0034
Ordering Information
ICS9248yF-126-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
12
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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